I've just started learning VHDL and I decided to design a 4-bit universal shift register as a challenge. I want to approach the component structurally, as opposed to behaviourally. I've got pretty much all of the system design done (multiplexers, flip-flops and top module all compile fine), however the register seems to only be able to parallel. In general a shift register is characterized by the following control and data signals, which are fully recognized by XST: clock serial input. Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock, asynchronous clear, serial in, and serial out.
- Listing 8.10 universal shift register-library ieee;use ieee.stdlogic1164.all;entity shiftregister isport(clk, reset: in stdlogic;ctrl: in stdlogicvector(1 downto 0);d: in stdlogicvector(3 downto 0);q: out stdlogicvector(3 downto 0));end shiftregister;architecture twosegarch of shiftregister issignal rreg: stdlogicvector(3 downto 0);signal rnext: stdlogicvector(3 downto 0);begin- registerprocess(clk,reset)beginif (reset='1') thenrreg '0');elsif (clk'event and clk='1') thenrreg.